1. Field of Invention
The invention relates to the technology associated with a layout of a driver of liquid crystal display (LCD), and more particularly to an integrated circuit for static random access memory (SRAM) standby power reduction in LCD driver.
2. Related Art
FIG. 1 is a system block diagram of the liquid crystal display (LCD) according to the prior art. Referring to FIG. 1, the LCD includes a display panel 101, a source driver 102, a gate driver 103 and a timing controller 104, wherein the timing controller 104 includes an embedded frame buffer 105. General speaking, since the driver of the LCD with the high resolution has a embedded frame buffer 105 and the stored data of the frame buffer 105 should be maintained in the wait state or the idle state, the large power consumption thereof is generated, where the main reason to generate the power consumption is to refresh frame so as to frequently access the embedded frame buffer 105 of the driver of the LCD.
In order to reduce the power consumption of the display panel, a memory in pixel (MIP) technology is provided. This technology can achieve the very lower power consumption when the frame does not change or the partial frame change. Further, the MIP technology is used for storing a partial data, such as most significant bit (MSB), into the pixel or sub-pixel. The MIP technology can be used for replacing one bit or three bits of each pixel data, wherein each pixel data generally includes 24 bits (each R, G, B data respectively includes 8 bits data). As above, the color representation of the LCD can be still maintained and the LCD system does not need to frequently access the frame buffer 105. Thus, the dynamic power consumption can be reduced.
For example, in the power saving mode, such as the wait state or the idle state, the LCD only need the MSB of each R, G, B pixel data. In addition, it is assumed that the LCD only displays a timepiece in the wait state. Originally the frame buffer 105 should be accessed 60 times per second. Since the MIP technology is provided, and the second hand of the timepiece moves once per second, the frame buffer 105 can be accessed once per second to refresh the memory unit of the MIP.
The abovementioned technology can effectively reduce the accessed time of the frame buffer 105. However, in the wait state, only the MSB is accessed, the remained seven least significant bits (LSB) does not be accessed. When the seven LSBs stored in the frame buffer 105 does not be accessed, the frame buffer 105, the leakage current of the frame buffer 105 becomes the main issue of the power consumption.
In order to further reduce the power consumption of the LCD system, the present invention provides a new layout of the SRAM circuit.